Question about refreshing DDR RAM for video application.

[SingSing]

I am working on a chip that used to have 640x480 VGA output. There are just enough internal RAM to happily support that resolutiion.

I updated the video controller with option of 800x600 and 1024x768. But not so fast, there are now NOt enough internal RAM to support the added resolution. Okay, I went outside the chip and add a 16 bits wide DDR RAM to support the video. Since it is DDR, then I got 32 bits of data per cycle, that's great.

For video refresh rate at 60Hz, come with a period of 16.67ms, and that will force the entire video bit maps to be read out, and that served the function of DRAM refresh.

What about retaining the video if the chip loss power or go into standby ? Standard DDR RAM supports self-refresh and auto-refresh. Can any of these modes use to retain the memory content with only DDR powered ?

I don't really get how self-refresh work and achieve the refresh. Can some one help me out, on explain it ?


Note : The need is 8192 refresh cycle per 64ms.

[aedipuss]

start over again. what exactly is the problem? is this concerning the p4 3.6 you list in your computer details?

what is the video card??? there hasn't been one that only did 640x480 in ten years at least.

you can't add just one memory board and get DDR to work. it only functions with matched pairs of chips.

and no, all data is lost if power goes out at all. ram used in a computer needs constant power.

forget the math. you don't understand enough about the inner workings of a computer.

[SingSing]

This is not about computer.

[redwudz]

For that type of technical information, you might try a Google search for ' refreshing ddr ram white papers ' and you may find what you want. There's a lot of info out there, though, so it might take a bit of digging.

I'm assuming you are working with a stand alone video controller?

[SingSing]

I am working on a motion controller chip. In order to figure out why the chip, react a certain way, the common approach is hook it to a PC via a communication port, and see the internal states of the chip, on the PC monitor.

But why not bypass the PC, and just put the result right on the LCD monitor ? That's what I did!

I used three 8-bits wide memory array to hold the R,G,B video information, and clock it out with H-sync,V-sync,dots, thru a video DAC. That works great for 640x480 graphics. Wiith a character rom table, I also can mixed the text in as soft-fon.

I looked at the published VGA timings , and find out I can easily add 800x600, and 1024x768, with just changing the counts, and I tested the new design with color bars with those wonderful LCD monitors, which always able to sync to almost anythings.

I now try to support my new video controller with external DDR as video RAM. I just can't figured out how to keep this external video RAM intact, while the chip is taking time to re-configure for a new motion sequence.

I did google about DDR refresh on the web, but they are all taking to each other who already understand how DDR refresh actually work. Those information did not make sense to me who is a newbie in DDR memory.

Since almost all video controller use off-the-shelf VRAM, which is like DDR. A person that work on this type of subject must already know how to deal with it. A good hint will be really helpful to me.

[jagabo]

You can refresh DRAM simply by reading it with the CPU. Many (very) old computers did this. DRAM controllers usually include logic to perform the refresh independent of the CPU. You can refresh rows with RAS-only strobes, or CAS before RAS strobes.

http://download.micron.com/pdf/technotes/DT30.pdf

I don't know about self refresh in DDR DRAM. It might be programmed via some pullup/pulldown resistors at boot time.

DDR datasheet:
http://wiki.laptop.org/images/4/43/A2S56D40CTP-G5.pdf

Micron.com has lots of datasheets.

[SingSing]

In page 28 of the second document talks about "async self refresh" , that can be enter with CKe/RAS/CAS/WE pull to their respective state, It did not said when the chip HAVE to exit this mode. Can someone confirms the memory content will stay intact, until I re-apply clk, assert NOP, and etc.. ?

If I setup the DDR in auto-refresh mode for exceeded long time, then the refresh counter will just roll over. Hey they can't be any harm in ove refresh. But I have to kludge a clock in to clock the auto-fresh cycle, which is hard to arrange.

[SingSing]

Just for the record. I settled for Micron compatible 16Megx16 ( aka 4 bank x 4 meg x 16 ) DDR SDRAM. I stored the last known RGB bit maps in a NOR flash, before power down. This allow the equipment to be powered down, and moved to another point of interest.

I found out the most requested mode is text and graphics mode in single color in 640x480. The right 160 column pixels are used for text, and the left 480x480 pixels are used for graphics map. This configuration are used in several control chips. User like the simple access to both text and graphics portions. Higher resolution are supported, but the additional effort to program the large bit map, often cause users to choose the low-res text/graphics mode !

Now, I can look inside my chip even with a $99.00 15in LCD monitor with NO software involved!